Structure and manufacturing method of a chip scale package

ABSTRACT

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

This application is a continuation of Ser. No. 09/837,007, filed on Apr.18, 2001, which is a continuation-in-part of Ser. No. 09/798,654, filedon Mar. 5, 2001, now U.S. Pat. No. 6,818,545.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices,and more particularly, to a method and package for packagingsemiconductor devices.

(2) Description of the Prior Art

Semiconductor device performance improvements are largely achieved byreducing device dimensions, a development that has at the same timeresulted in considerable increases in device density and devicecomplexity. These developments have resulted in placing increasingdemands on the methods and techniques that are used to access thedevices, also referred to as Input/Output (I/O) capabilities of thedevice. This has led to new methods of packaging semiconductor deviceswhereby structures such as Ball Grid Array (BGA) devices and Column GridArray (CGA) devices have been developed. A Ball Grid Array (BGA) is anarray of solder balls placed on a chip carrier. The balls contact aprinted circuit board in an array configuration where, after reheat, theballs connect the chip to the printed circuit board. BGA's are knownwith 40, 50 and 60 mil spacings. Due to the increased deviceminiaturization, the impact that device interconnects have on deviceperformance and device cost has also become a larger factor in packagedevelopment. Device interconnects, due to their increase in length inorder to package complex devices and connect these devices tosurrounding circuitry, tend to have an increasingly negative impact onthe package performance. For longer and more robust metal interconnects,the parasitic capacitance and resistance of the metal interconnectionincrease, which degrades the chip performance significantly. Ofparticular concern in this respect is the voltage drop along power andground buses and the RC delay that is introduced in the critical signalpaths.

One of the more recent developments that is aimed at increasing theInput-Output (I/O) capabilities of semiconductor device packages is thedevelopment of Flip Chip Packages. Flip-chip technology fabricates bumps(typically Pb/Sn solders) on aluminum pads on a semiconductor device.The bumps are interconnected directly to the package media, which areusually ceramic or plastic based. The flip-chip is bonded face down tothe package medium through the shortest paths.

In general, Chip-On-Board (COB) techniques are used to attachsemiconductor die to a printed circuit board, these techniques includethe technical disciplines of flip chip attachment, wirebonding, and tapeautomated bonding (TAB). Flip chip attachment consists of attaching aflip chip to a printed circuit board or to another substrate. A flipchip is a semiconductor chip that has a pattern or arrays of terminalsthat are spaced around an active surface area of the flip chip, allowingfor face down mounting of the flip chip to a substrate.

Generally, the flip chip active surface has one of the followingelectrical connectors: BGA (wherein an array of minute solder balls iscreated on the surface of the flip chip that attaches to the substrate);Slightly Larger than Integrated Circuit Carrier (SLICC) (which issimilar to the BGA but has a smaller solder ball pitch and diameter thanthe BGA); a Pin Grid Array (PGA) (wherein an array of small pins extendssubstantially perpendicularly from the attachment surface of a flipchip, such that the pins conform to a specific arrangement on a printedcircuit board or other substrate for attachment thereto. With the BGA orSLICC, the solder or other conductive ball arrangement on the flip chipmust be a mirror image of the connecting bond pads on the printedcircuit board so that precise connection can be made.

The invention addresses concerns of creating a BGA type package wherebythe pitch of the solder ball or solder bump of the device interconnectis in the range of 200 μm or less. The conventional, state-of-the-artsolder process runs into limitations for such a fine interconnect padpitch, the invention provides a method and a package for attachingdevices having very small ball pitch to an interconnect medium such as aPrinted Circuit Board.

SUMMARY OF THE INVENTION

A principle objective of the invention is to provide a method forapplying fine pitch solder bumps directly to the I/O pads of asemiconductor device, without a redistribution interface, and bondingthe semiconductor device directly to a Ball Grid Array substrate usingthe flip-chip bonding approach.

Another objective of the invention is to provide a method for shorteningthe interconnection between a semiconductor device and the substrate onwhich the device is mounted, thus improving the electrical performanceof the device.

Yet another objective of the invention is to eliminate conventionalmethods of re-distribution of device I/O interconnect, thereby makingpackaging of the device more cost-effective and eliminating performancedegradation.

A still further objective of the invention is to improve chipaccessibility during testing of the device, thus eliminating the needfor special test fixtures.

A still further objective of the invention is to improve performance anddevice reliability of BGA packages that are used for the mounting ofsemiconductor devices having small-pitch I/O interconnect bumps.

A still further objective of the invention is to perform Chip ScalePackaging (CSP) without re-distribution, including for various paddesigns such as peripheral or central pad designs.

A still further objective of the invention is to provide a method ofmounting small-pitch semiconductor devices in such a manner that fluxremoval and the dispensing of device encapsulants is improved.

In accordance with the objectives of the invention a new method andpackage is provided for the mounting of semiconductor devices that havebeen provided with small-pitch Input/Output interconnect bumps. Finepitch solder bumps, consisting of pillar metal and a solder bump, areapplied directly to the I/O pads of the semiconductor device, the deviceis then flip-chip bonded to a substrate. Dummy bumps may be provided forcases where the I/O pads of the device are arranged such that additionalmechanical support for the device is required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross section of a prior art Ball Grid Array package, thesemiconductor device is enclosed in a molding.

FIG. 2 shows a cross section of a prior art Ball Grid Array package,underfill is provided for the semiconductor device.

FIG. 3 shows a cross section of a first solder bump that has beencreated in accordance with the above referenced continuation-in-partapplication, this drawing has been extracted from thecontinuation-in-part application for reference purposes.

FIG. 4 shows a cross section of a second solder bump that has beencreated in accordance with the above referenced continuation-in-partapplication, this drawing has been extracted from thecontinuation-in-part application for reference purposes.

FIG. 5 shows a cross section of the BGA package of the invention, thesemiconductor device is encapsulated in a molding compound.

FIG. 6 shows a cross section of the BGA package of the invention,underfill is provided to the semiconductor device.

FIG. 7 shows a top view of an array type I/O pad configuration of asemiconductor device.

FIG. 8 shows a top view of a peripheral type I/O pad configuration of asemiconductor device.

FIG. 9 shows a top view of a center type I/O pad configuration of asemiconductor device.

FIG. 10 shows a top view of a center type I/O pad configuration of asemiconductor device, dummy solder bumps have been provided in supportof the semiconductor device.

FIG. 11 shows a top view of the substrate with exposed I/O contact pads,this exposure is accomplished by not depositing the solder mask in closeproximity to the contact pads of the semiconductor device.

FIG. 12 shows a cross section of the substrate of FIG. 11.

FIG. 13 shows a top view of a prior art substrate with exposed I/Ocontact pads, the solder mask is in close proximity to the contact padsof the semiconductor device.

FIG. 14 shows a cross section of the substrate of FIG. 13.

FIGS. 15 a through 15 f show examples of applications of the invention.

FIGS. 16 a and 16 b demonstrate how the invention leads to the abilityto reduce the pitch between I/O pads.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The above stated objective of improving chip accessibility duringtesting of the device, thus eliminating the need for special testfixtures, can further be highlighted as follows. The disclosed method ofthe invention, using Chip Scale Packaging (CSP), can control the cost oftesting CSP devices by keeping the same body size of the chip and byusing the same size substrate. For conventional CSP packages, the chipmay have different body sizes, which imposes the requirement ofdifferent size test fixtures. With the continued reduction of the sizeof semiconductor devices, additional and varying device sizes areexpected to be used. This would result in ever increasing costs forback-end testing of the devices in a production environment. Theinvention provides a method where these additional back-end testingcosts can be avoided.

Referring now to FIG. 1, there is shown a cross section of a typicalflip chip package with the semiconductor device being encapsulated in amolding compound. The Integrated Circuit (IC) device 10 enters theprocess as a separate unit with the contact points (balls 16) attachedto the bottom of the chip 10. The IC 10 is placed on the surface of aBGA substrate 12, an (optional) interconnect substrate 14 has beenprovided for additional routing of the electrical network to whichdevice 10 is attached. The balls 18 that are connected to the lowersurface of the substrate 12 make contact with surrounding circuitry (notshown). The paths of electrical interconnect of device 10 as shown incross section in FIG. 1 is as follows: contact pumps (points of I/Ointerconnect, not shown in FIG. 1) are provided on the surface of devicethat faces substrate 12, contact balls 16 are connected to these contactbumps. Contact balls 16 interface with points of contact (contact pads)provided in the surface of the (optional) interconnect network 14 or,for applications where the interconnect interface 14 is not provided,with points of contact (contact pads) provided in the surface of theBall Grid Array (BGA) substrate 12. BGA substrate 12 may further havebeen provided with one or more layers of interconnect metal, all of theinterfaces (the interconnect substrate 12 and the optionalredistribution lines provided in BGA substrate 12) result ininterconnecting balls 16 with balls 18. Balls 18 are the contact pointsthat connect the package that is shown in cross section in FIG. 1 tosurrounding circuitry.

Whereas the cross section that is shown in FIG. 1 shows contact balls 16for the establishment of contacts between device 10 and the underlyingsubstrate 12, some prior art applications still used wire bondconnections (not shown in FIG. 1), this in order to achieve optimumelectrical performance of the device package.

Further shown in the cross section of FIG. 1 is layer 19, which may beprovided over the surface of semiconductor device 10 facing thesubstrate 12. This re-distribution layer provides interconnect linesover the surface of device 10 and is required in prior art applicationsif solder bumps are required on current pad layout for wire bondingpurposes. The main purpose of the redistribution layer is to enlarge thepitch of solder bump interconnects if the bond pads are originallydesigned for wire bonding applications. It will be clear from laterexplanations that the invention removes the need for the redistributionlayer.

FIG. 2 shows a cross section of a conventional BGA package whereby thesemiconductor device 10 is provided with underfill 22, no moldingcompound (20, FIG. 1) has been provided in the package that is shown incross section in FIG. 2. All the other statements that relate to theelectrical interconnection of the device 10 of FIG. 2 are identical tothe statements that have been made in the description provided for thepackage of FIG. 1. It should be noted in FIG. 2 that the sides of theunderfill 22 are sloping such that the physical contact between theunderfill 22 and the substrate 12 is extended beyond the dimensions ofthe bottom surface of the chip 10. This is a normal phenomenon withliquid underfill, which enhances the mechanical strength between thesubstrate 12 and the IC chip 10.

Referring now to FIG. 3, there is shown a cross section of a firstsolder bump that has been created in accordance with the abovereferenced continuation-in-part application, this drawing has beenextracted from the continuation-in-part application for referencepurposes. The elements that are shown in FIG. 3 that form part of thesolder bump of the continuation-in-part application are the following:

-   10, a semiconductor surface such as the surface of a substrate-   30, a layer of dielectric that has been deposited over the    semiconductor surface 10-   32, contact pads that have been created on the surface of the layer    30 of dielectric-   34, a patterned layer of passivation that has been deposited over    the surface of the layer 30 of dielectric; openings have been    created in the layer 34 of passivation, partially exposing the    surface of contact pads 32-   36, an isotropically etched layer of barrier metal; because this    layer of barrier metal has been isotropically etched, the barrier    metal has been completely removed from the surface of the layer 34    of passivation except where the barrier metal is covered by the    overlying pillar metal (38) of the solder bump-   38, the pillar metal of the solder bump-   40, a layer of under bump metal created overlying the pillar metal    38 of the solder bump, wherein the distance between an edge of the    under bump metal layer and an edge of the metal pillar of the solder    bump is greater than 0.2 microns-   42, the solder metal.

The cross section that is shown in FIG. 4 is similar to the crosssection of FIG. 3 with the exception of layer 35, which is ananisotropically etched layer of barrier metal (etched after the solderbump 42 has been created) which, due to the nature of the anisotropicetch, protrudes from the pillar metal 38 as shown in the cross sectionof FIG. 4.

The cross sections that are shown in FIGS. 3 and 4 and that have beenextracted from the above referenced continuation-in-part applicationhave been shown in order to highlight that the referenced applicationprovides of method of creating:

-   a fine-pitch solder bump    -   smaller solder bumps    -   a fine-pitch solder bump of high reliability due to the        increased height of the solder bump    -   a cost-effective solder bump by using standard solder material        and eliminating the need for expensive “low-a solder”    -   a solder bump that allows easy cleaning of flux after the        process of flip chip assembly and before the process of        underfill and encapsulation    -   a solder bump which allows easy application of underfill.

Referring now to the cross section that is shown in FIG. 5, there isshown a cross section of the BGA package of the invention whereby thesemiconductor device has been encapsulated in a molding compound. Theelements that are highlighted in the cross section of FIG. 5 are thefollowing:

-   50, a semiconductor device that is mounted in the package of the    invention shown in cross section in FIG. 5-   52, the (BGA) substrate on the surface of which device 50 is mounted-   54, the pillar metal of the interface between the device 50 and the    BGA substrate 52, similar to pillar metal 38 of FIGS. 3 and 4-   56, the solder bump of the interface between the device 50 and the    BGA substrate 52, similar to solder bump 42 of FIGS. 3 and 4-   58, the contact balls that are used to interconnect the package of    the invention with surrounding circuitry-   60, molding compound into which the device 50 is embedded for    protection against the environment.

The columns 54 of pillar metal typically have a height of between about10 and 100 μm and more preferably about 50 μm.

The cross section that is shown in FIG. 6 is identical to the crosssection of FIG. 5 with the exception of the underfill 62 which is usedin stead of the molding compound 60 of FIG. 5.

To further relate the above referenced continuation-in-part applicationwith the present invention, the following comment applies: the creationof the pillar metal 54 and the solder bump 56 starts using the I/Ocontact pads of device 50 (not shown in FIGS. 5, 6) as the contact pads;that is the I/O contact pads of device 50 take the place of the contactpad 32 of FIGS. 3 and 4 in the creation of the pillar metal 54 and thesolder bump 56. The process of creating the pillar metal 54 and thesolder bump 56 therefore is as follows:

-   a layer of dielectric is deposited over the active surface of device    50; the active surface of device 50 is the surface in which I/O    contact points have been provided; this surface will face the BGA    substrate 52 after mounting of the device 50 on BGA substrate 52-   openings are created in the layer of dielectric, exposing the I/O    contact pads of device 50; this brings the process of the invention    to the point of the continuation-in-part application where contact    pads 32 (FIGS. 3, 4) have been created on the surface of the layer    30 of dielectric-   a layer of passivation is deposited over the surface of the layer of    dielectric, similar to layer 34, FIGS. 3, 4-   openings are created in the layer of passivation, partially exposing    the surface of the device I/O contact pads-   a barrier layer is deposited over the surface of the layer of    passivation, identical to layer 36, FIGS. 3, 4-   the pillar metal 54 of the solder bump is formed, identical to layer    38, FIGS. 3, 4-   the layer of under bump (not shown in FIGS. 5, 6) is created    overlying the pillar metal, identical to layer 40, FIGS. 3, 4-   the solder bump 56 is formed, identical to layer 42, FIGS. 3, 4-   the layer of barrier metal is isotropically (FIG. 3) or    anisotropically (FIG. 4) etched.

These above highlighted steps of creating the pillar metal and thesolder bump are provided by the referenced continuation-in-partapplication using the processing steps that have been detailed above andthat are in accordance with the referenced continuation-in-partapplication. Details of these processing steps will therefore not befurther highlighted as part of the present application.

Referring now to FIG. 7, there is shown a top view of an array typearrangement of I/O contact points 66 that form the contact points ofdevice 50. This top view of the array type contact points 66 is shown asone example of where the process of creating pillar metal and solderbumps can be applied.

FIGS. 8 and 9 show two more examples of arrangements of I/O contactpads, that are provided on the surface of device 50, where the processof the invention can be applied. FIG. 8 shows a peripheral I/O paddesign 68 while FIG. 9 shows a center type pad design 70.

While the peripheral I/O pad design that is shown in FIG. 8 providesevenly distributed mechanical support for device 50, this is not thecase for the center pad design that is shown in FIG. 9. For this kind ofdesign, additional mechanical support can be provided to device 50, thisis shown in top view in FIG. 10. The elements highlighted as 70 in FIG.10 are the solder bumps that have been created on the I/O contact padsof device 50, elements 72 are dummy solder bumps that can be provided inorder to lend mechanical support to device 50. The symmetry of the dummybumps 72 as shown in FIG. 10 makes clear that device 50 is, with thedummy bumps 72, adequately and symmetrically supported.

In mounting semiconductor devices on the surface of a BGA substrate, itis important from a manufacturing point of view that solder flux, afterthe process of solder flow has been completed, can be readily removed.This requires easy access to the surface areas of the BGA substratewhere solder flux has been able to accumulate. In addition, the deviceinterconnects (consisting of pillar metal and solder bumps) must, afterthe pillar metal and the solder bumps have been formed in accordancewith the continuation-in-part application, be readily available so thatdevice encapsulants can be adequately applied. More importantly, afterflip-chip assembly and solder reflow, the flux that has accumulated inthe gap between the semiconductor die and the substrate must be cleaned.For these reasons, it is of value to apply the solder mask not acrossthe entire surface of the substrate (blank deposition) but to leave openthe surface areas of the substrate that are immediately adjacent to theI/O interconnects (of pillar metal and solder bumps). This design willcreate a channel though which the cleaning solution can flow easily.This is highlighted in the top view of FIGS. 11 and 12, where is shown:

-   52, the BGA substrate on the surface of which device 50 (not shown)    is mounted-   74, I/O contact pads provided on the surface of substrate 52-   76, interconnect traces provided on the surface of substrate 52,    connected with contact pads 74-   79, the surface region of the substrate 52 over which no solder mask    is applied-   80, the surface region of the substrate 52 over which a solder mask    is applied.

This is further highlighted in the cross section of substrate 52 that isshown in FIG. 12. It is clear that over the region 79, which is theregion where no solder mask is applied, the metal pads 74 are readilyavailable so that removal of solder flux and the dispensing ofencapsulants can be performed. It must be remembered that this ispossible due to the height of the combined pillar metal 54 and thesolder bump 56, which results in adequate spacing between the device 50and the surface of substrate 52. Further shown in FIG. 12 are routingtraces 82 that are provided on the surface of substrate 52 foradditional interconnect.

FIGS. 13 and 14 show how prior art procedures and conventions areapplied to affect flux removal and encapsulant application. In the priorart application, the metal pads 74 are typically surrounded by thesolder mask 78, even for small pitch I/O pad designs. Typically, thesolder mask is determined by the type of contact pad design (FIGS. 7through 9), whereby the contact pads 74 require about 60 μm clearancefor reasons of proper alignment registration. This results in thesubstrate design rule being more critical, allowing for less error andsmaller tolerance in the design parameters. In addition, the height ofthe solder mask 78 is generally about 10 μm larger than the height ofthe contact pad 74, further forming an obstacle in applying moldingcompound or in removing flux after the solder process has beencompleted. These aspects of the prior art are shown in FIGS. 13 and 14,where the metal pads 74 are completely surrounded by the solder mask 78.The present invention negates the highlighted negative effects of thesolder mask on flux cleaning and on dispensing molding compound.

FIGS. 15 a through 15 f show examples of applications of the invention,as follows:

FIG. 15 a shows the application of a solder mask over the surface thathas previously been shown in FIG. 7, the solder mask has been indicatedwith cross-hatched regions 90, the regions where no solder mask ispresent have been highlighted with 91.

FIG. 15 b and 15 c relate to the previous FIG. 8, the solder mask hasbeen highlighted as regions 90 while the regions where no solder mask ispresent have been highlighted with 91. The design that is shown in FIG.15 c is considered a “partial” peripheral type I/O pad configuration ofa semiconductor device since I/O pads 68 are only provided along twoopposing sides of the semiconductor device 50.

It must be noted that the designs that are shown in FIGS. 15 b and 15 ccan further be provided with supporting dummy solder bumps in theregions of the solder mask 90, these supporting solder bumps have notbeen shown in FIGS. 15 b and 15 c.

FIG. 15 d shows the design that has previously been shown in FIG. 9,FIG. 15 e shows a design that is similar to the design of FIG. 15 d withthe exception that the contact points 70 have now been provided in twocolumns. It is clear from these two drawings that channels have beencreated in the solder mask that are in line with and include the contactpads. These channels allow for easy flow of cleaning fluid and thereforeallow for easy removal of solder flux after the process of chipencapsulation and solder flow has been completed.

FIG. 15 f relates to the previously shown FIG. 10, the above observationrelating to the creation of a channel through the solder flux and thetherefrom following easy flow of cleaning fluid equally applies to thedesign that is shown in FIG. 15 f.

FIGS. 16 a and 16 b demonstrate how the invention leads to the abilityto reduce the pitch between I/O pads.

FIG. 16 a shows how in prior art applications the solder mask 90 isprovided, further shown in FIG. 16 a are:

-   94, the circumference of the opening that is created in the solder    mask 90-   95, the circumference of the bond pad on the surface of a    semiconductor device-   92, the distance (or spacing) S between two adjacent contact pads-   93, the diameter D of a contact pad.

In prior art applications as shown in FIG. 16 a, the pitch betweenadjacent contact pads is P=D+S+2× (the required clearance betweenadjacent contact pads). The required clearance is needed by the soldermask and requires that extra space is required between the circumference95 of the contact pad and the circumference 94 of the opening created inthe solder mask.

With the wide channel created by the invention through the solder mask,highlighted as channel 91 in FIG. 16 b, the conventional clearance isnot required, resulting in the ability to reduce the pitch betweenadjacent contact pads 95. This leads to a distance 92′, FIG. 16 b, whichis smaller than distance 92 of FIG. 16 a.

Although the invention has been described and illustrated with referenceto specific illustrative embodiments thereof, it is not intended thatthe invention be limited to those illustrative embodiments. Thoseskilled in the art will recognize that variations and modifications canbe made without departing from the spirit of the invention. It istherefore intended to include within the invention all such variationsand modifications which fall within the scope of the appended claims andequivalents thereof.

1. A chip package comprising: a ball grid array (BGA) substrate having afirst surface and a second surface opposite to said first surface; asemiconductor device comprising a passivation layer and a first padexposed by an opening in said passivation layer, wherein saidpassivation layer comprises polymer, and wherein said first padcomprises copper; a copper pillar between said first pad and said firstsurface, wherein said copper pillar has a height between 10 and 100micrometers; a barrier metal layer between said first pad and saidcopper pillar, wherein said barrier metal layer is on said first pad,over said passivation layer and in said opening, wherein said barriermetal layer comprises titanium; a solder metal between said copperpillar and said first surface, wherein said solder metal is joined withsaid ball grid array (BGA) substrate; an underfill between saidsemiconductor device and said first surface, wherein said underfillcontacts with said semiconductor device and said first surface andencloses said copper pillar and said solder metal; and a contact ball onsaid second surface.
 2. The chip package of claim 1 further comprising anickel layer between said copper pillar and said solder metal, whereinsaid nickel layer has a thickness between 1 and 10 micrometers.
 3. Thechip package of claim 1, wherein said passivation layer comprisespolyimide.
 4. The chip package of claim 1 further comprising a metallayer between said copper pillar and said solder metal, wherein saidmetal layer comprises a first portion over said copper pillar and asecond portion overhanging said copper pillar.
 5. The chip package ofclaim 1, wherein said ball grid array (BGA) substrate comprises a soldermask and a second pad separate from said solder mask, wherein saidsecond pad is at a same horizontal level as said solder mask, andwherein said second pad has a circular shape.
 6. A chip packagecomprising: a substrate; a semiconductor device comprising a passivationlayer and a first pad exposed by an opening in said passivation layer,wherein said passivation layer comprises polymer, and wherein said firstpad comprises copper; a copper pillar between said first pad and saidsubstrate, wherein said copper pillar has a height between 10 and 100micrometers; a barrier metal layer between said first pad and saidcopper pillar, wherein said barrier metal layer is on said first pad,over said passivation layer and in said opening, wherein said barriermetal layer comprises titanium; a solder metal between said copperpillar and said substrate, wherein said solder metal is joined with saidsubstrate; and an underfill between said semiconductor device and saidsubstrate, wherein said underfill contacts with said semiconductordevice and said substrate and encloses said copper pillar and saidsolder metal.
 7. The chip package of claim 6 further comprising a nickellayer between said copper pillar and said solder metal, wherein saidnickel layer has a thickness between 1 and 10 micrometers.
 8. The chippackage of claim 6, wherein said passivation layer comprises polyimide.9. The chip package of claim 6 further comprising a metal layer betweensaid copper pillar and said solder metal, wherein said metal layercomprises a first portion over said copper pillar and a second portionoverhanging said copper pillar.
 10. The chip package of claim 6, whereinsaid substrate comprises a solder mask and a second pad separate fromsaid solder mask, wherein said second pad is at a same horizontal levelas said solder mask, and wherein said second pad has a circular shape.11. A chip package comprising: a ball grid array (BGA) substrate havinga first surface and a second surface opposite to said first surface; asemiconductor device comprising a passivation layer and a first padexposed by an opening in said passivation layer, wherein said first padcomprises copper; a copper pillar between said semiconductor device andsaid first surface, wherein said copper pillar is connected to saidfirst pad through said opening, and wherein said copper pillar has aheight between 10 and 100 micrometers; a solder metal between saidcopper pillar and said first surface, wherein said solder metal isjoined with said ball grid array (BGA) substrate; an underfill betweensaid semiconductor device and said first surface, wherein said underfillcontacts with said semiconductor device and said first surface andencloses said copper pillar and said solder metal; and a contact ball onsaid second surface.
 12. The chip package of claim 11, wherein saidpassivation layer comprises silicon nitride.
 13. The chip package ofclaim 11, wherein said passivation layer comprises polymer.
 14. The chippackage of claim 11 further comprising a nickel layer between saidcopper pillar and said solder metal, wherein said nickel layer has athickness between 1 and 10 micrometers.
 15. The chip package of claim11, wherein said ball grid array (BGA) substrate comprises a solder maskand a second pad separate from said solder mask, wherein said second padis at a same horizontal level as said solder mask, and wherein saidsecond pad has a circular shape.
 16. A chip package comprising: asubstrate; a semiconductor device comprising a passivation layer and afirst pad exposed by an opening in said passivation layer, wherein saidfirst pad comprises copper; a copper pillar between said semiconductordevice and said substrate, wherein said copper pillar is connected tosaid first pad through said opening, and wherein said copper pillar hasa height between 10 and 100 micrometers; a solder metal between saidcopper pillar and said substrate, wherein said solder metal is joinedwith said substrate; and an underfill between said semiconductor deviceand said substrate, wherein said underfill contacts with saidsemiconductor device and said substrate and encloses said copper pillarand said solder metal.
 17. The chip package of claim 16, wherein saidpassivation layer comprises silicon nitride.
 18. The chip package ofclaim 16, wherein said passivation layer comprises polymer.
 19. The chippackage of claim 16 further comprising a nickel layer between saidcopper pillar and said solder metal, wherein said nickel layer has athickness between 1 and 10 micrometer.
 20. The chip package of claim 16,wherein said substrate comprises a solder mask and a second pad separatefrom said solder mask, wherein said second pad is at a same horizontallevel as said solder mask, and wherein said second pad has a circularshape.